This summary covers a new era in which the semiconductor industry — after half a century of making things smaller — has hit the limits of that approach, and where the "bridge" connecting chips to one another and the "foundation" supporting them now take center stage. It explains how transparent glass is emerging as a new solution at the heart of this shift, what kind of future glass could enable, and what obstacles must still be overcome. By the end, you'll have a clear picture of why glass is drawing attention as the next-generation semiconductor substrate, and what technological advances lie ahead. 😊

1. The End of the Shrinking Era: The Nanometer Wars Are Over 📉

For the past 50 years, humanity has been obsessed with making semiconductors smaller. Shrinking transistors to 10 nanometers, 5 nanometers, even 3 nanometers was the defining measure of progress. But physics ultimately issued its cold verdict:

"We can't make them any smaller."

Faced with that wall, people began to think differently.

"If we can't make individual units smaller, what if we combine multiple units into something larger?"

That single question changed the rules of the game entirely. The focus shifted away from the microscopic circuitry inside a chip and toward the "bridge" connecting chips to each other and the "foundation" supporting them all. The nanometer wars are over — the micrometer (μm) wars have begun. And standing squarely in the center of that new battlefield is transparent glass.

2. The Limits of Chip Size and the Yield Problem: The End of the Monolithic Chip 🚧

AI models keep growing, and the number of transistors that must be packed onto a chip keeps climbing. Fitting more transistors means making the chip larger — but there is an insurmountable ceiling called the reticle limit. With current technology, the maximum area onto which light can print a circuit pattern is approximately 858 mm², and NVIDIA's GH100 die already reaches 814 mm², essentially brushing against that limit.

Beyond size, there is another problem. Imagine drawing chips like a grid of squares on a large canvas. Dip a small brush in paint and flick it — every square the droplet touches becomes defective. With small squares, most survive untouched. But what happens when the squares grow large? A single tiny droplet can ruin the whole thing. The larger the square, the more sharply the survival rate falls.

This is the yield problem. Caught between "can't go smaller" and "can't go bigger," the monolithic chip ceased to be a viable answer.

3. The Dawn of the Chiplet Era: Assembling Like LEGO 🧱

So the industry moved in the opposite direction. Imagine trying to 3D-print Hogwarts Castle in one shot — if anything goes wrong mid-print, you throw the whole thing away. But build it out of LEGO, and a single bad brick is just swapped out.

Chiplets are exactly that LEGO concept. Instead of one massive chip, you divide it into smaller pieces, manufacture each separately, and then reassemble them into one unit. Smaller chips have higher yields, cutting costs, and they don't run into the reticle limit. Even better, each chiplet can be made on a different process node — the core compute die on cutting-edge 3 nm, and the I/O circuitry on cheaper 6 nm. A very sensible arrangement.

NVIDIA's Blackwell combines two near-maximum-size dies into a single GPU; Intel's Ponte Vecchio assembles 47 chiplets into one processor.

But there is a critical price to pay.

Inside a monolithic chip, everything is connected by internal wiring — fast and efficient. The moment you split the chip, communication that once happened internally must now cross the chip boundary. It is as if a team that held in-person meetings in one building is suddenly scattered across different locations, forced to video-call each other.

The quality of those video calls determines the entire team's productivity. If the connections between chiplets are not as fast as the original internal wiring, there was no point splitting the chip in the first place.

Making a great chip is no longer enough on its own. The era of connecting chips well has arrived.

4. The Role of the Substrate and CoWoS: The McMuffin Architecture 🍔

The structure that holds chiplets together resembles an Egg McMuffin — without the top bun. 😋

The bottom English muffin is the substrate — the foundation that supports everything. It supplies power to the chips, connects the package to the outside world, and physically holds the whole assembly together.

The bacon on top represents the chips — the GPU, HBM memory, and other components that actually perform computation.

When there was only one chip, you just laid the bacon on the muffin and you were done. In the chiplet era, however, the bacon slices need to talk to each other. So an egg layer (the interposer) was added between the muffin and the bacon. This interposer acts as a high-speed bridge connecting chip to chip.

You've probably heard the acronym CoWoS — Chip-on-Wafer-on-Substrate. Here C is the chip (bacon), W is the interposer (egg), and S is the substrate (muffin). The name itself describes the structure.

In this architecture, the key question becomes: "What do we make the egg and the muffin out of?" That decision determines performance, cost, and how many AI chips the world can actually produce.

5. The Limits of Organic Substrates: A Throne Shaken by the AI Era 👑

To understand this story properly, you need to know who currently holds the throne.

Today, the vast majority of substrates are organic substrates — layers of resin and fiberglass laminated together. Stable and inexpensive. Since displacing ceramic substrates in the late 1990s, organic substrates have quietly underpinned the semiconductor industry for 25 years.

Twenty-five years is enough time for almost everything to change. Transistors shrank from hundreds of nanometers to 3 nm; chip performance improved by tens of thousands of times. But substrates? They kept doing their job quietly, with the same basic materials.

AI shattered that quiet. 💥

To understand the problem, you need to know the two tests a good substrate must pass.

1. Survive the heat: All materials expand when heated. When an AI accelerator consumes hundreds of watts and heats up, both the chip (silicon) and the substrate beneath it expand — but at different rates. This is like two runners with different stride lengths competing in a three-legged race. The ratio of these expansion rates is called the coefficient of thermal expansion (CTE). Organic substrates expand 6–7 times more than silicon. In small packages that was manageable, but as AI chip packages grow larger, the warping becomes catastrophic. In the worst case, solder joints crack.

   

2. Protect the signal: As electrical signals travel through the substrate, the substrate material absorbs signal energy. Think of a car driving on a dirt road — fine at low speed, but at the ultra-high frequencies AI chips demand, signals blur beyond recognition. Restoring those blurred signals puts excessive load on DSPs (digital signal processors), which consume power and generate heat, which further degrades signals — a vicious cycle. This is the same physical barrier as the copper limitations discussed in the context of photonic interconnects.

   

For 25 years, organic substrates passed both tests comfortably. Packages were small, speeds were modest. But in front of AI chips, both tests collapsed simultaneously.

The throne began to wobble. 📉

6. The Silicon Interposer: The Best Bridge, But the Biggest Bottleneck 🌉

The first place organic substrates buckled was in the intermediate layer that directly connects chip to chip — the interposer. The organic material simply couldn't handle the volumes of high-speed signal traffic this bridge required.

In 2012, TSMC's answer was straightforward:

"Use silicon — the same material chips are made from — to build the bridge."

This is the heart of CoWoS. A silicon slab is placed between the chips as the interposer. Because it's the same silicon, the thermal expansion mismatch is reduced. And because it's manufactured with semiconductor processes, wiring finer than a human hair becomes possible. Without the silicon interposer, today's AI chips would not exist.

The problem is that silicon interposers are made on semiconductor wafers. They don't require leading-edge process nodes, but they still compete for TSMC's cleanrooms, wafer capacity, and packaging lines.

Back to the McMuffin analogy: if a kitchen has only four burners and two of them are busy frying eggs (interposers), there aren't enough burners left to cook all the bacon (chips) you need. Making the bridge competes for the same resources as making the chips. That is the essence of the bottleneck. 😬

The cost is steep as well. A single large silicon interposer easily exceeds $100, and the interposer alone can account for more than half the total packaging cost. By 2028, packaging a single top-tier AI chip is expected to cost around $1,300.

Size runs into limits too. Silicon interposers are cut from round wafers, so the same yield logic applies: the larger the interposer, the fewer you get per wafer and the higher the defect rate.

Silicon accomplished what organic substrates could not — but at too high a price. At the moment AI chip demand is exploding, the best bridge has become the biggest bottleneck.

Organic substrates are cheap but buckle under AI chips; silicon interposers deliver top performance but consume too many packaging resources and resist scaling. Between the two lay a vacancy.

That is exactly where glass steps in. ✨

7. The Rise of Glass: Two Solutions 🧪

"Glass substrate" is a broad term, but in practice two entirely distinct paths coexist.

1. Path 1: Replace the interposer with glass. The bridge (interposer) that silicon occupied is instead fabricated using the large-area glass processing equipment developed by the display industry. In McMuffin terms, you swap the egg (interposer) for a material that needs no burner. Free up those burners and you can cook more bacon (chips). Samsung is targeting this path by 2028.

   

2. Path 2: Replace the substrate itself with glass. A fundamentally different logic — breaking through the performance limits of organic substrates at the most basic level. More expensive than organic substrates, but considered worth it. Intel has invested more than $1 billion in this path.

Same material, "glass" — but the problems each path is solving are different.

8. Glass's Overwhelming Advantages: Why Glass? 💎

Glass can make a compelling case by delivering overwhelming results on exactly the two tests where organic substrates failed.

1. Thermal expansion: Organic substrates expand at 17–20 ppm/°C; silicon at roughly 3 ppm/°C — a 6–7× gap. Glass can be tuned through composition to approach 3 ppm/°C, matching silicon's stride. This is the most fundamental advantage. Package sizes that were impossible with organic substrates become achievable on glass.

2. Signal loss: If an organic substrate is a dirt road, glass is freshly laid asphalt. Signal loss through glass can be more than 10× lower than through an organic substrate. Less signal blur means less burden on recovery circuitry, lower power consumption, less heat generation — and the vicious cycle is broken.

Those two advantages alone are significant, but glass has two additional properties organic substrates can never match.

1. Exceptionally smooth surface: If an organic substrate's surface is a dirt road, a glass surface is an ice rink. Hybrid bonding — a new technique that joins copper pads directly without solder — requires exactly this kind of smoothness. It shrinks the gap between connection points from tens of micrometers to under 10 micrometers, enabling tens of times more connections per unit area. Impossible on organic substrates, possible on glass.

   

2. Transparency: Glass lets light through. This means optical waveguides can be embedded directly inside the substrate. The optical interconnects discussed in the context of photonic chips can be extended from the chip surface down into the substrate itself — a world where electrical signals convert to optical signals and travel between chips through glass. Glass can be the foundation of that world.

9. The Challenges Facing Glass: Three Mountains to Climb ⛰️⛰️⛰️

Of course, if glass were a perfect solution it would already sit on the throne. 😅

Start with the most fundamental problem: glass breaks. Micro-cracks can form during cutting, drilling, and handling. When chips power on and off tens of thousands of times — expanding and contracting with each cycle — those cracks can propagate catastrophically. The industry is working to suppress this through edge-finishing techniques and strengthening treatments, but long-term reliability data across thousands of thermal cycles is still scarce.

Thermal conductivity is two orders of magnitude lower than silicon's. Silicon conducts roughly 130–150 W/m·K; glass manages only about 1 W/m·K. Yet there is an interesting twist to this weakness. Remember glass's transparency? If waveguides are embedded in the substrate and data travels as light, signals passing through the substrate generate almost no heat. The low thermal conductivity stops being a fatal flaw. Glass's weakness and the strength of optical interconnects complement each other.

There is another paradox. The very property that makes glass excellent for signals — that it doesn't absorb them — creates an unexpected weakness for power delivery. In a noisy café, neighboring chatter dissolves into background noise. But in an empty concert hall, a single cough echoes throughout the room. A glass substrate is that empty concert hall. Minute noise from power supply circuits bounces around rather than being absorbed, causing the power supply to ripple instead of flowing cleanly.

Reliability, heat dissipation, power noise — three mountains stand before glass. Feasibility has been demonstrated in the lab, but these mountains must be climbed before glass can reach mass-production lines.

10. Conclusion: The Future of the Substrate Wars and Glass's Potential ✨

The blade that once divided transistors has grown dull. In its place, the needle and thread that stitches chips together grows ever sharper. Substrates are no longer simple plastic pedestals — they have become massive circuits that determine the performance ceiling of the entire system, a second semiconductor in their own right.

By 2028, glass will begin taking its place at the heart of cutting-edge AI accelerators. And beyond that, a world awaits where light flows through glass, electrical signals convert to optical signals, and chips communicate across photonic pathways.

The potential has been confirmed. But between the lab glass and the factory production line, many mountains remain. Trillions of won in capital are moving right now to cross them.

Who will be first to clear the mass-production threshold, and whose capital will prove to be the real capital — that grand financial map will unfold in Part 2. 💰

References

• Chip size limits and chiplet architecture
  • NVIDIA, "H100 Tensor Core GPU Architecture" (March 2022)
  • NVIDIA, GTC 2024 Keynote, Blackwell Architecture (March 2024)
  • Intel, "Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing" (ISSCC 2022)
• Packaging technology
  • TSMC, "CoWoS® Platform"
  • SemiAnalysis, "AI Scaling – CoWoS and HBM Supply Chain Analysis" (July 2023)
  • Bloomberg Intelligence, "Advanced Semiconductor Packaging Market Could Reach $80B by 2033" (October 2025)
• Glass substrate technology and material properties
  • Intel, Press Release, "Intel Unveils Industry-Leading Glass Substrates to Meet Demand for More Powerful Computing" (September 2023)
  • Semiconductor Engineering, "Glass Substrates Gaining Momentum"
  • MDPI, "Review of Glass Substrate Technology"
• Key industry developments
  • NIST / U.S. Department of Commerce, "Preliminary Agreement with Absolics" (2024)
  • Samsung Electro-Mechanics, "MOU with Sumitomo Chemical Group for Glass Core Joint Venture"
  • TrendForce, "Reports of Intel Beginning Glass Substrate Licensing" (2025)
• Market outlook
  • Bloomberg Intelligence, "Advanced Semiconductor Packaging Market" (October 2025)
  • Future Markets Inc., "Global Market for Glass Substrates for Semiconductors 2026–2036"